The present invention relates to a nonvolatile semiconductor memory and particularly relates to a nonvolatile semiconductor memory used as a multi-level NAND cell type EEPROM, e.g., a four-level NAND cell type EEPROM.
There is known, as one of nonvolatile semiconductor memories, an NAND cell type EEPROM. This EEPROM has a memory cell array consisting of a plurality of NAND cell units. Each of the NAND cell units consists of a plurality of memory cells connected in series and two select transistors connected to both ends of the memory cells, respectively. The NAND cell unit is connected between a bit line and a source line.
Each memory cell consists of an n channel MOS transistor having a so-called stack gate structure in which a control gate electrode is stacked on a floating gate electrode. Each select transistor consists of an n channel MOS transistor having a structure in which an upper electrode is stacked on a lower electrode as in the case of the memory cell. It is the lower electrode, for example, that actually functions as the gate electrode of the select transistor.
One source region or one drain region is common to adjacent two transistors among a plurality of transistors (memory cells and select transistors) in an NAND cell unit.
Now, the concrete structure of an NAND cell type EEPROM will be described.
FIG. 1 shows part of a memory cell array of the NAND cell type EEPROM.
Each NAND cell unit consists of a plurality of (4, 8, 16 or the like) memory cells connected in series and two select transistors connected to both ends of the memory cells, respectively. The NAND cell unit is connected between bit lines BLi and source lines SL. Each of the source lines is connected to reference potential lines each formed of a conductive member such as polysilicon at preset positions.
The source lines SL extend in row direction, whereas the bit lines BLi and the reference potential lines extend in column direction. Contact portions on which the source line SL and the reference potential line contact are provided at intervals at which each source line SL intersects, for example, 64 bit lines, i.e., four bit lines BL0, . . . BL63. The reference potential lines is connected to so-called peripheral circuits provided on the peripheral section of the memory cell array.
Word lines (control gate lines) WL1, . . . and WLn extend in the row direction and the select gate lines SG1 and SG2 extend in the row direction, as well. The collection of the memory cells connected to one word line (control gate line) WLi is called one page. Further, the collection of the memory cells connected to the word lines WL1, . . . and WLn put between the two select gate lines SG1 and SG2 is called one NAND block or simply one block.
One page consist of, for example, 256-byte (256×8) memory cells. The memory cells in one page are programmed almost simultaneously. In addition, if one page consists of 256-byte memory cells and one NAND cell unit consists of eight memory cells, one block consists of 2048-byte (2048×8) memory cells. The memory cells in one page are erased almost simultaneously.
FIG. 2 is a plan view of one NAND cell unit in the memory cell array. FIG. 3 is a cross-sectional view of the NAND cell taken along line of FIG. 2. FIG. 4 is a cross-sectional view thereof taken along line IV-IV of FIG. 2. FIG. 5 shows an equivalent circuit of the devices of FIGS. 2 to 4.
In a p substrate (p-sub) 11-1, a so-called double-well region, consisting of an n well region (Cell n-well) 11-2 and p well region (Cell p-well) 11-3, is formed. The memory cells and select transistors are formed in the p well region 11-3.
The memory cells and select transistors are arranged in an element region within the p well region 11-3. The element region is surrounded by an element separation oxide film (element separation region) 12 formed on the p well region 11-3.
In this example, one NAND cell unit consists of eight memory cells M1 to M8 connected in series and two select transistors S1 and S2 connected to the both ends of the memory cells, respectively.
Each memory cell consists of a silicon oxide film (gate insulating film) 13 formed on the p well region (Cell p-well) 11-3, a floating gate electrode 14 (141, 142 . . . 148) on the silicon oxide film 13, a silicon oxide film (inter-polysilicon insulating film) 15 on the floating gate electrode 14 (141, 142 . . . 148), a control gate electrode 16 (161, 162 . . . 168) on the silicon oxide film 15 and a source-drain region 19 in the p well region (Cell p-well) 11-3.
Each select transistor consists of a silicon oxide film (gate insulating film) formed on the p well region 11-3, a gate electrode 14 (149, 1410) and 16 (169, 1610) on the silicon oxide film, and a source-drain region 19 in the p well region 11-3.
The structure of the select transistor is similar to that of the memory cell for the following reason. By simultaneously forming the memory cells and the select transistors through the same process, the number of process steps is intended to be reduced to thereby reduce production cost.
One source region (n+ diffused layer) 19 or one drain region (n+ diffused layer) 19 is common to adjacent two transistors among the plural transistors (memory cells and select transistors) in the NAND cell unit.
The memory cells and the select transistors are covered with a silicon oxide film (CVD oxide film) 17 formed by the CVD method. A bit line 18 connected to one end of the NAND cell unit (n+ diffused layer 19) is arranged on the CVD oxide film 17.
FIG. 6 shows the well structure of the NAND cell type EEPROM.
In the p substrate (p-sub) 11-1, a so-called double-well region, consisting of the n well region (Cell n-well) 11-2 and the p well region (Cell p-well) 11-3, an n well region (n-well) 11-4 and a p well region (p-well) 11-5.
The double-well region is formed on a memory cell array section, and the n well region 11-4 and the p well region 11-5 are formed on a peripheral circuit section.
The memory cells are formed in the p well region 11-3. The n well region 11-2 and the p well region 11-3 are set to have the same potential.
A high voltage n channel MOS transistor applied with a higher voltage than a power supply potential is formed on the p substrate (p-sub) 11-1. A low voltage p channel MOS transistor applied with the power supply voltage is formed on the n well region (n-well) 11-4 and a low voltage n channel MOS transistor applied with the power supply voltage is formed on the p well region (p-well) 11-5.
Next, the basic operation of the NAND cell type EEPROM will be described.
First, to facilitate the description, the following preconditions are specified. Two level data “0” and “1” are stored in a memory cell; a state in which the threshold voltage of the memory cell is low (e.g., the threshold voltage is negative) is a “0” state; and a state in which the threshold voltage of the memory cell is high (e.g., the threshold voltage is positive) is a “1” state.
In an ordinary two-level NAND cell type EEPROM, a state in which the threshold voltage of the memory cell is low is set at a “1” state and that in which the threshold voltage is high is set at a “0” state. However, as will be described later, the present invention is mainly intended for a multi-level (e.g., four-level) NAND type EEPROM. Considering this, it is assumed that a state in which the threshold voltage of the memory cell is low is a “0” state and that in which the threshold voltage of the memory cell is high is a “1” state.
As for the memory cell, it is assumed that the “0” state is an erase state and the “1” state is a program state. “Programming” involves “0”-programming and “1”-programming. The “0”-programming means maintaining the erase state (“0” state) and the “1”-programming means changing the “0” state to the “1” state.
Program Operation
In program operation, the potential of a bit line is set according to program data on a selected memory cell connected to the bit line. For example, if the program data is “1” (“1”-programming), the potential of the bit line is set at a ground potential (0V) Vss. If the program data is “0” (“0”-programming), the potential of the bit line is set at a power supply potential Vcc.
The potential of a select gate line SG1 at a bit line side (drain side) in a selected block, i.e., in an NAND cell unit including the selected memory cell is set at the power supply potential Vcc. The potential of a select gate line SG2 at a source line side in the selected block, i.e., in the NAND cell unit including the selected memory cell is set at the ground potential (0V) Vss.
The potentials of select gate lines SG1 and SG2 in the unselected block, i.e., in the NAND cell unit not including the selected memory cell are all set at the ground potential (0V) Vss.
In case of “1”-programming, the ground potential (0V) Vss is transmitted to the channel of the selected memory cell in the selected block. In case of “0”-programming, the channel potential of the selected memory cell in the selected block is Vcc−Vthsg (where Vthsg is the threshold voltage of the select transistor S1). Thereafter, the channel of the selected memory cell in the selected block turns into a floating state while maintaining the potential Vcc−Vthsg so as to cut off the select transistor S1 at the bit line side (drain side) in the selected block.
If the selected memory cell is not the closest to the bit line and the threshold voltage of a memory cell positioned at the bit line side with respect to the selected memory cell (or, at least one memory cell among a plurality of memory cells which exist at the bit line side with respect to the selected memory cell) is a positive voltage Vthcell, then the channel of the selected memory cell turns into a floating state while maintaining the potential Vcc−Vthcell.
Then, a program potential Vpp (e.g., about 20V) is applied to a selected word line in the selected block, i.e., to the control gate electrode of the selected memory cell. An intermediate potential Vpass (e.g., about 10V) is applied to unselected word lines in the selected block, i.e., the control gate electrodes of unselected memory cells.
At this moment, the channel potential of the selected memory cell to which “1”-programming is conducted, is the ground potential (0V) Vss. Due to this, a high voltage necessary for the “1”-programming is applied between the floating gate electrode and the channel (Cell p-well) of the memory cell and electrons move from the channel to the floating gate electrode by F-N tunnel effect. As a result, the threshold voltage of the selected memory cell rises (e.g., moves from a negative value to a positive value).
On the other hand, the channel potential of the selected memory cell to which “0”-programming is conducted, is Vcc−Vthsg or Vcc−Vthcell and the channel is in a floating state. Due to this, if either Vpp or Vpass is applied to the word line, the channel potential rises by the capacitive coupling between the control gate electrode and the channel. As a result, a high voltage necessary for “1”-programming is not applied between the floating gate electrode and the channel (Cell p-well) and the threshold voltage of the selected memory cell is kept in a present status (the memory cell is kept in an erase state).
Erase Operation
Data erase is carried out in block units and data on memory cells in a selected block are erased almost simultaneously.
Concrete erase operation will be described below.
First, the potentials of all word lines (control gate electrodes) in a selected block are set at 0V and the potentials of all word lines (control gate electrodes) of unselected blocks and all select gate lines in all blocks are set at an initial potential Va and then set in a floating state.
Thereafter, a high voltage Vpp (e.g., about 20V) is applied to the p well region (Cell p-well) and the n well region (Cell n-well) for erase operation.
At this moment, as for the memory cells in the selected block, since the potentials of the word lines (control gate electrodes) are 0V and those of the well regions are VppE, a sufficiently high voltage is applied between the control gate electrodes and the well regions for erase operation.
Accordingly, in the memory cells in the selected block, electrons in the floating gate electrodes move to the well regions and the threshold voltages of the memory cells decrease (e.g., the threshold voltages become negative) by the F-N tunnel effect.
On the other hand, the potentials of all word lines in the unselected blocks rise from the initial potential Va to VppE or a potential close to VppE by the capacitive coupling between the word lines and the well regions. Likewise, the potentials of all select gate lines in all blocks rise from the initial potential Va to VppE or a potential close to VppE by the capacitive coupling between the select gate lines and the well regions.
Accordingly, in the memory cells in the unselected blocks, a high voltage sufficient for data erase is not applied between the control gate electrodes and the well regions. That is, since electrons within the floating gate electrodes do not move, the threshold voltages of the memory cells have no change (the present state is maintained).
Read Operation
Data read is carried out by changing the potentials of bit lines according to memory cell data and by detecting the potential change.
First, a bit line (or part of bit lines if all bit lines or a bit line shield read method or the like is adopted) to which a memory cell which data is to be read is connected, is precharged, the potential of the bit line is set at a precharge potential, e.g., the power supply potential Vcc and the bit line is then turned into a floating state.
Thereafter, the potential of the selected word line, i.e., the potential of the control gate electrode of the selected memory cell is set at 0V, those of unselected word lines (or the control gates of unselected memory cells) and of the select gate lines are set at the power supply potential Vcc (e.g., about 3V), and those of the source lines are set at 0V.
At this time, if selected memory cell data is “1” (the threshold voltage Vth of the memory cell satisfies Vth >0), the selected memory cell is turned off and the potential of the bit line to which this memory cell is connected is, therefore, kept a precharge potential (e.g., the power supply potential Vcc).
On the other hand, if the selected memory cell data is “0” (the threshold potential Vth of the memory cell satisfies Vth <0), the selected memory cell is turned on. As a result, the charges of the bit line to which the selected memory cell is connected are discharged and the potential of the bit line decreases from the precharge potential by ΔV.
In this way, the potential of the bit line changes according to the memory cell data. Thus, if this change is detected by a sense amplifier circuit, the memory cell data can be read.
Meanwhile, so-called multi-level NAND cell type EEPROMs have been developed and put to practical use with a view of increasing one-chip memory capacity and reducing cost per bit.
In case of the above-stated NAND cell type EEPROM, binary (one-bit) data (“0”, “1”) can be stored in a memory cell. An n-level NAND cell type EEPROM, where n is a natural number of not lower than 3 is, by contrast, characterized in that n-level data can be stored in a memory cell.
In case of an four-level NAND cell type EEPROM, for example, four-level (2-bit) data (“00”, “01”, “10”, “11”) can be stored in a memory cell.
The prior art multi-level NAND cell type EEPROM is described in, for example, Reference 1 (Japanese Patent Application No. 8-98627).
Normally, in the n-level NAND cell type EEPROM, a plurality of latch circuits are provided per bit line connected to a selected memory cell. Namely, if n-level data are programmed into or read from a selected memory cell, the plural latch circuits function to temporarily store the n-level data.
As described in Reference 1, for example, in the four-level NAND cell type EEPROM, two latch circuits corresponding to one bit line connected to a selected memory cell are provided so as to temporarily store four-level (two-bit) data during program or read operation.
However, as shown, for example, in FIG. 7, each latch circuit consists of SRAM (static RAM) cells. Further, the latch circuit consisting of the SRAM cells is large in area. In addition, if the quantity of data stored in one memory cell increases (the value of n is higher), the number of latch circuits provided per bit line connected to the selected memory cell increases, as well.
In case of the four (=22)-level NAND cell type EEPROM, for example, two latch circuits are provided per bit line connected to a selected memory cell. In an eight (=23)-level NAND cell type EEPROM, three latch circuits are provided per bit line connected to a selected memory cell.
Accordingly, if data stored in the memory cell are multi-level (n-level) data and the number of n increases, the number of latch circuits (SRAM cells) on a memory chip increases and the area of the chip disadvantageously increases.